2015•Unpublished venueRequires access

Sandwiched-gate inverter: Novel device structure for future logic gates

Myunghwan Ryu, Franklin Bien, Young‐Min Kim

Abstract

In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed.

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Available abstract

Key concepts: Inverter, NMOS logic, Noise margin, PMOS logic, Logic gate, Electronic engineering, Transient (computer programming), Noise (video)