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2002•Unpublished venueRequires access

A parallel trimming method of offset reduction for comparators and amplifiers

Ming Zhang, F. Devos, J.-F. Pône, Yang Ni

Open publisher page 2 citations

Abstract

In this work, we have proposed a parallel trimming method for analogue circuits based on a tunnel analogue memory in CMOS standard technology. This method can be used to trim simultaneously a large number of circuits with a global control of trimming and a local control of charge injection automatically. The experimental results show that this parallel trimming is efficient and exploitable for CMOS standard technology.>

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What this paper is about

In this work, we have proposed a parallel trimming method for analogue circuits based on a tunnel analogue memory in CMOS standard technology. This method can be used to trim simultaneously a large number of circuits with a global control of trimming and a local control of charge injection automatically. The experimental results show that this parallel trimming is efficient and exploitable for CMOS standard technology.>

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OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

In this work, we have proposed a parallel trimming method for analogue circuits based on a tunnel analogue memory in CMOS standard technology. This method can be used to trim simultaneously a large number of circuits with a global control of trimming and a local control of charge injection automatically. The experimental results show that this parallel trimming is efficient and exploitable for CMOS standard technology.>

Key concepts: Trimming, CMOS, Offset (computer science), Electronic circuit, Computer science, Comparator, Amplifier, Electronic engineering

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