Comparator offset calibration using unbalanced clocks for high speed and high power efficiency
Shiuh-Hua Wood Chiang
Abstract
Shiuh-Hua Wood Chiang
Abstract
A novel comparator offset calibration using unbalanced clocks is proposed. The new technique avoids loading the comparator core with trimming elements, thus maximising the comparator speed and power efficiency. Simulations show that a comparator utilising the proposed calibration achieves near‐native speed and noise performance. It also achieves superior energy‐delay‐noise product over comparators with conventional calibrations.
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A novel comparator offset calibration using unbalanced clocks is proposed. The new technique avoids loading the comparator core with trimming elements, thus maximising the comparator speed and power efficiency. Simulations show that a comparator utilising the proposed calibration achieves near‐native speed and noise performance. It also achieves superior energy‐delay‐noise product over comparators with conventional calibrations.
Key concepts: Comparator, Offset (computer science), Comparator applications, Calibration, Power (physics), High-gain antenna, Computer science, Electronic engineering