Improved base-collector depletion charge and capacitance model for SiGe HBT on thin-film SOI
Xu Xiao-Bo, Zhang He-Ming, Huiyong Hu
Abstract
Xu Xiao-Bo, Zhang He-Ming, Huiyong Hu
Abstract
The SiGe heterojunction bipolar transistor (HBT) on thin film SOI is successfully integrated with SOI CMOS by folded collector. This paper deals with the collector depletion charge and the capacitance of this structure. An optimized model is presented based on our previous research. The results show that the charge model is smoother, and that the capacitance model with considering different current flow areas, is vertical and horizontal depletion capacitances in series, showing that the depletion capacitance is smaller than that of a bulk HBT. The charge and capacitance vary with the increase of reverse collector-base bias. This collector depletion charge and capacitance model provides valuable reference to the SOI SiGe HBT electrical parameters design and simulation such as Early voltage and transit frequency in the latest 0.13 m SOI BiCMOS technology.
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The SiGe heterojunction bipolar transistor (HBT) on thin film SOI is successfully integrated with SOI CMOS by folded collector. This paper deals with the collector depletion charge and the capacitance of this structure. An optimized model is presented based on our previous research. The results show that the charge model is smoother, and that the capacitance model with considering different current flow areas, is vertical and horizontal depletion capacitances in series, showing that the depletion capacitance is smaller than that of a bulk HBT. The charge and capacitance vary with the increase of reverse collector-base bias. This collector depletion charge and capacitance model provides valuable reference to the SOI SiGe HBT electrical parameters design and simulation such as Early voltage and transit frequency in the latest 0.13 m SOI BiCMOS technology.
Key concepts: Capacitance, Heterojunction bipolar transistor, Materials science, Silicon on insulator, Optoelectronics, Depletion region, CMOS, Parasitic capacitance