dRAM Design Using the Taper-Isolated Dynamic RAM Cell

The TI dRAM cell, a MOSFET with two dynamically programmable threshold states, is very attractive for VLSI dRAM's because of its potential 3X density advantage over the one-transistor and -capacitor (1-T) cell, 10X lower leakage at high temperatures compared to the 1-T cell, and its immunity to soft errors. Linear scaling of the 1-T cell by a factor k reduces the available signal by ~k/sup 3/, whereas the charging current for the TI RAM cell is invariant to scaling since the W/L ratio remains constant allowing it to scale to higher density. An experimental array (64 rows by 8 columns), representing a cross section of a 16K dRAM, with on-chip decoding and sensing has been fabricated using the TI RAM cell as the memory element, Using 4-spl mu/m design rules, the cell size was 204 /spl mu/m/sup 2/ due to pitch requirements for the decoder and sense amplifier. This compares with 170-200 /spl mu/m/sup 2/ for the 1-T cell using 2.5-/spl mu/m design rules being fabricated in the 64K dRAM's today. The array which is compatible with 5-V-only operation was designed to provide diagnostic capability rather than speed and shows the data can be accessed 85-100 ns after the CAS signal, In this paper, the physics of the TI RAM cell are discussed as well as circuit considerations for its implementation into an array.