6.8–10 GHz frequency synthesizer for software-defined-radio
Hsiao‐Chin Chen, Shey‐Shi Lu
Abstract
Hsiao‐Chin Chen, Shey‐Shi Lu
Abstract
A 6.8–10 GHz fractional-N frequency synthesizer for the software-defined-radio is presented in 90-nm CMOS technology. Differentially tuned varactors are employed to achieve a VCO with a wide tuning range and low phase noise. The charge pump current is varied to optimize the loop bandwidth over the entire VCO tuning range from 6.8 GHz to 10 GHz. The power dissipation of the synthesizer chip is 59 mW. The synthesizer achieves the close-in phase noise of −91 dBc/Hz and the reference spur of −68 dBc at the integer-N mode. The synthesizer can settle to the desired frequency within 10∼11 us in each application band while offering a frequency resolution of 3 Hz.
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A 6.8–10 GHz fractional-N frequency synthesizer for the software-defined-radio is presented in 90-nm CMOS technology. Differentially tuned varactors are employed to achieve a VCO with a wide tuning range and low phase noise. The charge pump current is varied to optimize the loop bandwidth over the entire VCO tuning range from 6.8 GHz to 10 GHz. The power dissipation of the synthesizer chip is 59 mW. The synthesizer achieves the close-in phase noise of −91 dBc/Hz and the reference spur of −68 dBc at the integer-N mode. The synthesizer can settle to the desired frequency within 10∼11 us in each application band while offering a frequency resolution of 3 Hz.
Key concepts: Frequency synthesizer, dBc, Phase noise, Voltage-controlled oscillator, Phase-locked loop, Direct digital synthesizer, CMOS, Electronic engineering