Low-Power Logic Styles : CMOS vs CPL

Recently reported logic style comparisons based on full-adder circuits showed complementary pass-transistor logic (CPL) to be much more power efficient than conventional CMOS. New comparisons performed on more efficient CMOS circuit implementations and a wider range of different logic cells and by using realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, power dissipation, and power-delay (PT) products. 1 Introduction The increasing demand for low-power VLSI asks, among others, for power efficient logic styles [1]. Performance criteria for logic styles are circuit speed, circuit size, power dissipation, and wiring complexity as well as ease-of-use and generality of gates in cell-based design techniques. Dynamic logic styles are often a good choice for high-speed, but not for low-power circuit implementations due to the high node activity and large clock loads [1]. This paper focuses on static logic styles suitable for low-power im...