Leakage Power Reduction in CMOS Logic Circuits Using Stack ONOFIC Technique

Nowadays the power dissipation has become one of the problems of CMOS VLSI circuit design. High power dissipation is not regarded as good when it comes to the battery lifespan in the case of battery operated applications and alters things like reliability, cooling costs etc and high power dissipation also contributes in the reduction of battery life. Today's, leakage power dissipation is one of the most important issues in CMOS VLSI design. Designing of leakage free CMOS circuits is a challenging task. There are some effective techniques to reduce the power dissipation of CMOS VLSI circuits. In this work, we have proposed a circuit called stack ONOFIC technique to mitigate the leakage power in CMOS logic circuits. We have used various CMOS logic circuits like NAND, inverter, NOR to show the effect of the proposed technique in these circuits. In this paper, we have compared the various reduction technique with our proposed technique to show the comparative reduction in power dissipation and delay. We have used traditional (conventional), LECTOR, LCNT reduction techniques with the proposed technique and calculated the total power dissipation and delay of various CMOS logic circuits. All mentioned techniques have simulated in Mentor graphics tools with 130nm and 22nm technologies.