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Assembly reliability of CSPs with various chiip sizes by accelerated thermal and mechanical cycling test

Reza Ghaffarian

Abstract

A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

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Available abstract

Key concepts: Reliability (semiconductor), Temperature cycling, Scale (ratio), Reliability engineering, Variety (cybernetics), Test (biology), Government (linguistics), Chip

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Assembly reliability of CSPs with various chiip sizes by accelerated thermal and mechanical cycling test — Research Paper | ScholarLens