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A low phase noise fully integrated 2-GHz CMOS LC VCO design

Weixin Kong, H. C. Lin

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Abstract

This paper describes the design and analysis of a fully integrated CMOS Voltage Controlled Oscillators (VCO). The VCO is designed in TSMC 0.25µm single-poly, 5-metal CMOS process. It is designed to have a tuning range greater than 15% covering the frequency bands of WLAN 802.11b while consuming less than 7 mW of power. A generalized linear phase noise model is developed to predict VCO performance from circuit parameters. The model is used to optimize phase noise under power consumption constraint. The final VCO design achieves a low phase noise of-126 dBc/Hz at 1 MHz offset from carrier.

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What this paper is about

This paper describes the design and analysis of a fully integrated CMOS Voltage Controlled Oscillators (VCO). The VCO is designed in TSMC 0.25µm single-poly, 5-metal CMOS process. It is designed to have a tuning range greater than 15% covering the frequency bands of WLAN 802.11b while consuming less than 7 mW of power. A generalized linear phase noise model is developed to predict VCO performance from circuit parameters. The model is used to optimize phase noise under power consumption constraint. The final VCO design achieves a low phase noise of-126 dBc/Hz at 1 MHz offset from carrier.

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Available abstract

This paper describes the design and analysis of a fully integrated CMOS Voltage Controlled Oscillators (VCO). The VCO is designed in TSMC 0.25µm single-poly, 5-metal CMOS process. It is designed to have a tuning range greater than 15% covering the frequency bands of WLAN 802.11b while consuming less than 7 mW of power. A generalized linear phase noise model is developed to predict VCO performance from circuit parameters. The model is used to optimize phase noise under power consumption constraint. The final VCO design achieves a low phase noise of-126 dBc/Hz at 1 MHz offset from carrier.

Key concepts: Voltage-controlled oscillator, Phase noise, dBc, CMOS, Offset (computer science), Electronic engineering, Electrical engineering, Power consumption

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