Design of Fractional-N Frequency Synthesizer with Delta-Sigma Modulator for Wireless Mobile Communications

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of f ref /64. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a 0.5 ㎛ CMOS process with triple metal layers. The active chip area is about 4 ㎟ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.