ScholarLens Back to search
2003•Unpublished venueRequires access

A 5.8-GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications

Sau-Mou Wu, Ron‐Yi Liu, Weiliang Chen

Open publisher page 2 citations

Abstract

A 5.8-GHz fractional-N frequency synthesizer for IEEE 802.11a WLAN applications is designed in a 0.25mm CMOS process. The synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider and a digital third-order MASH delta-sigma modulator together. The VCO is capable of 240MHz tuning range and exhibits a phase noise of about -115dBc/Hz at 1MHz offset from the center frequency throughout the tuning range. The synthesizer has a bandwidth of 300KHz for a 35MHz reference and can achieve a close-in phase noise of about -80dBc/Hz while the total power consumption is 35mW from a single 2.5V supply.

About this research paper

What this paper is about

A 5.8-GHz fractional-N frequency synthesizer for IEEE 802.11a WLAN applications is designed in a 0.25mm CMOS process. The synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider and a digital third-order MASH delta-sigma modulator together. The VCO is capable of 240MHz tuning range and exhibits a phase noise of about -115dBc/Hz at 1MHz offset from the center frequency throughout the tuning range. The synthesizer has a bandwidth of 300KHz for a 35MHz reference and can achieve a close-in phase noise of about -80dBc/Hz while the total power consumption is 35mW from a single 2.5V supply.

Why it matters

OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

A 5.8-GHz fractional-N frequency synthesizer for IEEE 802.11a WLAN applications is designed in a 0.25mm CMOS process. The synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider and a digital third-order MASH delta-sigma modulator together. The VCO is capable of 240MHz tuning range and exhibits a phase noise of about -115dBc/Hz at 1MHz offset from the center frequency throughout the tuning range. The synthesizer has a bandwidth of 300KHz for a 35MHz reference and can achieve a close-in phase noise of about -80dBc/Hz while the total power consumption is 35mW from a single 2.5V supply.

Key concepts: Phase noise, Frequency synthesizer, Direct digital synthesizer, Voltage-controlled oscillator, Delta-sigma modulation, Frequency divider, IEEE 802.11a-1999, Electrical engineering

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
A 5.8-GHz delta-sigma fractional-N frequency synthesizer for IEEE 802.11a applications — Research Paper | ScholarLens