Precise Delay Generation using a Delay Chain Locked by Multiple Clock Period

This paper presents a new technique for generating precise clock delays. The technique can obtain finer timing resolution less than the gate delay of the delay chain by locking in multiple clock period. Using this technique, a 250ps of timing resolution could be achieved from a 750ps delay of the single delay stage in a DLL(Delay Locked Loop) structure. The delay chain of the proposed circuit is locked on three times of the clock period and a finer delay resolution than the absolute gate delay is achieved and verified through the simulation.