Estimation of Analog Layout Parasitics with Parameterized Polygons

Traditional analog integrated circuit design methodologies split circuit synthesisand physical layout design into different phases. Since analog circuits areusually very sensitive, physical layout effects, such as parasitics, can have significantinfluence on the performance and even the functionality of the design.Lack of considering layout effects in the circuit synthesis phase can result innumerous re-design iterations. Developing new analog design flows, methodologies,and automation tools are thus required in order to solve the problem.This research proposes a new analog circuit design flow which uses parameteri;:ed representation of physical layouts in order to estimate layout-inducedparasitics. A flexible description language for parameteri;:ed representation oflayouts has been developed. The description language is named GrammarBasedLayout Description (GBLD) and can be used to represent orthogonal andnon-orthogonal parameterized layouts, which are comprised mainly of parameterizedpolygons. We also developed algorithms for partitioning parameterizedpolygons so that accurate models of extracted circuits, which include models ofparasitics, can be generated automatically and efficiently. As a result, values oflayout-induced parasitics can be calculated or estimated on the fly in the circuitsynthesis process. Re-design iterations can thus be minimizecl.