Interprocessor bus specification for h/v-bus parallel processor simulation system

A functional specification is presented for the interprocessor bus in a parallel processor simulation system employing the horizontal/vertical-bus interprocessor communication merchanism (h/v-bus system). Six bus commands are defined to enable a bus controller to control operation of processing elements on its bus and to control data exchanges between the transfer memories of elements on the bus. Forty signals define an asynchronous interprocessor bus structure that can be incorporated into a h/v-bus system containing up to 64 processing elements. 5 references.