High-speed bus structures for multiprocessing

Parallel processing the application of several processors to a single task imposes stringent performance requirements on the bus structure used to connect the processors. This paper surveys several common bus architectures and presents an operational 64 megabytes per second synchronous bus supporting both data and control communications between processors. The bus also supports party lines, which allow messages to be sent to multiple destinations. An asynchronous version of the bus that supports data rates of 100 megabytes per second is also described. Introduction The designer of a high-speed distributed parallel processor must address four difficult issues: data transfer rates, provision for interunit communications, coordination of the processing between units, and network reliability. The bus structure used in the system affects all these issues. Parallel systems have used crossbar switches and separate control buses (1 to 3) to communicate between units. However, substantial system time overhead is incurred in those networks (4) with the selection of a ready task through a scheduler, the initialization of processors, communication delays when one task waits for the results from another, and system cleanup when a task finishes. The SPAN system (5,6) uses a single unidirectional ring bus to transfer software, data, and control between processor units. In addition, the bus structure permits the use of a unique software structure that allows the system to control all units, each operating at full capacity if required. A brief description of several of the more common bus structures provides an introduction to the options available to the system designer. The SPAN bus structure is then described as the starting point for understanding a unique asynchronous bus developed for systolic and wavefront array processors operating with data transfer rates of up to 100 megabytes per second. Bus Architectures