2024Unpublished venueRequires access

AI-Based RF-Input RF-Output Digital Predistortion Architecture for the Linearization of RF Power Amplifiers

Zhe Li, Yucheng Yu, Peng Chen, Ziming Wang, Chao Yu

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Abstract

In this paper, we propose an AI-based RF-input RF-output digital predistortion (AI-RIRO DPD) system that incorporates the strengths of both digital predistortion (DPD) and analog predistortion (APD) techniques, which is well-suited for scenarios where deploying a baseband DPD technique is unfeasible due to various constraints. The proposed hardware-friendly polyphase real-valued time-delay neural network (PRVTDNN) model is capable of linearizing multiple samples per clock cycle while avoiding the need for resource replication. The system prototype is demonstrated in FPGA with 983.04 MHz baseband sampling rates. Experiment results show a 14.47 dBc ACPR reduction for 40 MHz 5G-NR signal with a 3.5 GHz GaN power amplifier using the proposed model and hardware implementation.

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What this paper is about

In this paper, we propose an AI-based RF-input RF-output digital predistortion (AI-RIRO DPD) system that incorporates the strengths of both digital predistortion (DPD) and analog predistortion (APD) techniques, which is well-suited for scenarios where deploying a baseband DPD technique is unfeasible due to various constraints. The proposed hardware-friendly polyphase real-valued time-delay neural network (PRVTDNN) model is capable of linearizing multiple samples per clock cycle while avoiding the need for resource replication. The system prototype is demonstrated in FPGA with 983.04 MHz baseband sampling rates. Experiment results show a 14.47 dBc ACPR reduction for 40 MHz 5G-NR signal with a 3.5 GHz GaN power amplifier using the proposed model and hardware implementation.

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Available abstract

In this paper, we propose an AI-based RF-input RF-output digital predistortion (AI-RIRO DPD) system that incorporates the strengths of both digital predistortion (DPD) and analog predistortion (APD) techniques, which is well-suited for scenarios where deploying a baseband DPD technique is unfeasible due to various constraints. The proposed hardware-friendly polyphase real-valued time-delay neural network (PRVTDNN) model is capable of linearizing multiple samples per clock cycle while avoiding the need for resource replication. The system prototype is demonstrated in FPGA with 983.04 MHz baseband sampling rates. Experiment results show a 14.47 dBc ACPR reduction for 40 MHz 5G-NR signal with a 3.5 GHz GaN power amplifier using the proposed model and hardware implementation.

Key concepts: Predistortion, Amplifier, RF power amplifier, Linearization, Radio frequency, Power (physics), Electronic engineering, Computer science

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