Design of 16-Bit Sigma Delta ADC Modulator and its Digital Decimation Filter

In order to investigate the analog-to-digital converter (ADC) suitable for high-quality audio chips, a Sigma Delta modulator implemented using switched-capacitor technology and its digital decimation filter were designed. In this paper, a second-order 16-bit high-precision Sigma Delta modulator circuit is completed based on SMIC 0.18μm process. The digital filter structure is consist of a cascaded configuration of a Cascaded Integrator-Comb (CIC) filter, a compensation filter, and a half-band filter. The downsampling filter was simulated and verified using MATLAB and Modelsim platforms. Compared to traditional filter structures, this approach has the advantages of reduced hardware consumption and low power consumption. Overall mixed-level simulation of the Sigma Delta modulator circuit and decimation filter was conducted, yielding a signal-to-noise and distortion ratio (SNDR) of 100.9dB and an effective number of bits (ENOB) of 16 bits.