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2009•ITC-CSCC :International Technical Conference on Circuits Systems, Computers and CommunicationsRequires access

Sigma-Delta (Σ-Δ) ADC for Complex Sensor Applications

Sang-Yong Lee, Wonki Park, Kyongwon Min, Byong‐Deok Choi, SungChul Lee

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Abstract

In this paper, a sigma-delta (Σ-Δ) analog-to-digital converter (ADC) is presented with 14.97-bit accuracy. The ADC is composed of fourth-order single-loop single-bit sigma-delta (Σ-Δ) modulator and digital decimation filter. The modulator with an oversampling ratio of 128 and a signal bandwidth of 4㎑ has been designed in a 0.35㎛ CMOS technology. The designed decimation filter has been verified using an FPGA. The Σ-Δ modulator consumes 3㎽ from a single 3.3V supply voltage.

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What this paper is about

In this paper, a sigma-delta (Σ-Δ) analog-to-digital converter (ADC) is presented with 14.97-bit accuracy. The ADC is composed of fourth-order single-loop single-bit sigma-delta (Σ-Δ) modulator and digital decimation filter. The modulator with an oversampling ratio of 128 and a signal bandwidth of 4㎑ has been designed in a 0.35㎛ CMOS technology. The designed decimation filter has been verified using an FPGA. The Σ-Δ modulator consumes 3㎽ from a single 3.3V supply voltage.

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Available abstract

In this paper, a sigma-delta (Σ-Δ) analog-to-digital converter (ADC) is presented with 14.97-bit accuracy. The ADC is composed of fourth-order single-loop single-bit sigma-delta (Σ-Δ) modulator and digital decimation filter. The modulator with an oversampling ratio of 128 and a signal bandwidth of 4㎑ has been designed in a 0.35㎛ CMOS technology. The designed decimation filter has been verified using an FPGA. The Σ-Δ modulator consumes 3㎽ from a single 3.3V supply voltage.

Key concepts: Oversampling, Decimation, Delta-sigma modulation, CMOS, Electronic engineering, Analog-to-digital converter, Digital filter, Filter (signal processing)

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