CNTFET-based Approximate Ternary Adder Design

Multiple-Valued Logic (MVL) offers better data representation allowing higher information processing within the same amount of digits. With a trade-off in accuracy, approximate computation is a method to improve the power, size, and speed of digital circuits. This paper presents the design of CNTFET-based ternary half adder, full adder, 2-trit carry ripple adder, and 4trit carry ripple adder with different accuracies. The proposed designs are implemented using HSPICE tool and simulated for power consumption, delay, and error analysis. The trade-off between the transistor count and the computation accuracy of the propsoed designs is discussed. Simulation results show that the approximate and corrected approximate designs could significantly improve power-delay product and transistor count compared to their accurate designs. For some cases, approximate and corrected approximate designs have up to $19.8 \times$ improvement in the transistors count and up to $295.3 \times$ improvement in PDP compared to their accurate designs. The corrected designs outperform the approximate ones in terms of accuracy while achieving around $1.5 \times$ improvement in AED.