2015•IJSRD : international journal for scientific research and developmentRequires access

Design of Low Power Asynchronous Parallel Adder

Benedicta Roseline. R, S. Kamatchi

Abstract

This paper describes an asynchronous parallel adder. It is based on Radix method for faster computation of sum and to reduce delay caused by carry chain. The computation has been carried out using parallel process. The aim of this work is to reduce the Power Delay Product (PDP) and Energy Delay Product (EDP) of an adder. We use two Full Adders (FA) in a single block and use a carry look- ahead technique to shorten the carry path within the radix-4 FA block. To obtain low area, the carry is generated first and then it is reused in sum generation. The adder is implemented using Tanner EDA v13 tool. The practicality and superiority of the proposed technique have been verified by simulations over other asynchronous adders.

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Available abstract

Key concepts: Adder, Serial binary adder, Power–delay product, Carry-save adder, Asynchronous communication, Computer science, Carry (investment), Block (permutation group theory)