Design and Simulation of RISC Processor Using Verilog

Reduced Instruction Set Computer (RISC) Processors have recently become quite an important aspect of keeping up with all the advances in technology. This research presents a comprehensive study on the design and simulation of an improved RISC processor architecture on Field-Programmable Gate Arrays (FPGAs). The objective is to enhance the performance, efficiency, and versatility of RISC processors by incorporating novel design techniques and optimizations. The proposed design mainly focuses on the improved design of the Arithmetic and Logic Unit (ALU). The effectiveness of the proposed design is evaluated through extensive simulations. The results demonstrate significant improvements in performance in time and total power. The findings of this study indicate that the improved RISC processor design offers a promising approach to address the increasing demands of modern computing systems.