A complete design of a RISC processor for pedagogical purposes

In this paper we present the design of an instruction set architecture to address the need of providing a simple but realistic hands-on experience to computer organization and architecture students. To illustrate the goals of (Reduced Instruction Set Computer) RISC processors, we start with DLX architecture and show how we can apply the RISC philosophy and further reduce the DLX instruction set. At the end, students can build a complete pipelined processor in the lab with minimum cost using TTL chips. In this paper we give a recommendation to the chips needed to build this processor hoping that it would be useful for other Computer organization and architecture professors who want to provide their students with a deep insight on processor design.