Pre-silicon ASIC Library Validation

For standard cell design, it will go through ASIC regression with multiple design block. It can be high performance block design convergence, digital signal processing block, processor core design block as well as a few synthesis block. In most cases, the intention is to verify the standard cell collateral release is in good quality. However, the standard cell instantiation depends on the functionality in the design coding and timing constraint given. User has no control over the type of master cell as well as the overall standard cell coverage in all the design blocks running through the ASIC regression. In most cases, these regression focus on the process entitlement as well as potential physical design rule check as priority. This paper will share the general purpose standard cell ASIC regression design as well as methodology, in order to ensure high quality coverage on standard cell ASIC regression. Hopefully, the sharing will benefit the design community