Microelectronic Chip Attach With Silver Filled Epoxies: An Analytical and Experimental Study
K. J. Zwick, P. S. Ayyaswamy, I. M. Cohen
Abstract
K. J. Zwick, P. S. Ayyaswamy, I. M. Cohen
Abstract
Abstract In microelectronic chip packages, a mechanical bond between the chip and the leadframe is formed by depositing a pattern of epoxy drops on the lead frame, and then placing the chip on top of the epoxy. A small force is applied to the top of the chip which causes the epoxy to squeeze out under the chip and form a complete, void-free bond between the chip and the lead frame. In this paper, we analyze the squeezing flow of the bonding epoxy, and demonstrate that the bonding time is longer for large chips than for small chips. We also present the results of some related experiments on the squeezing flow of the epoxy. We find that the squeezing behavior predicted by our analysis agrees very well with the measured behavior under typical bonding conditions. Finally, we discuss two methods of reducing the bonding time, and the advantages and disadvantages associated with each of these methods.
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Abstract In microelectronic chip packages, a mechanical bond between the chip and the leadframe is formed by depositing a pattern of epoxy drops on the lead frame, and then placing the chip on top of the epoxy. A small force is applied to the top of the chip which causes the epoxy to squeeze out under the chip and form a complete, void-free bond between the chip and the lead frame. In this paper, we analyze the squeezing flow of the bonding epoxy, and demonstrate that the bonding time is longer for large chips than for small chips. We also present the results of some related experiments on the squeezing flow of the epoxy. We find that the squeezing behavior predicted by our analysis agrees very well with the measured behavior under typical bonding conditions. Finally, we discuss two methods of reducing the bonding time, and the advantages and disadvantages associated with each of these methods.
Key concepts: Microelectronics, Epoxy, Chip, Lead frame, Void (composites), Materials science, Wire bonding, Chip-scale package