Timing Regulation Scheme for RSFQ Circuit

Rapid single-flux-quantum (RSFQ) circuit requires an accurate timing scheme to maintain correct function, especially under a very high clock frequency. However, the reported timing regulation schemes have issues, including the bias margin of the circuit being small and the bias margin decrement caused by imprecise timing constraints. This article proposes a new timing regulation scheme based on clock-follow-data clocking that can solve the problems. The scheme uses the unique structure of the RSFQ circuit to eliminate the impact caused by different timing libraries and extend the biasing margin. The simulation results of the XOR gate under various timing regulation schemes demonstrated that the proposed scheme could obtain the maximum static timing analysis (STA) bias margin. Also, the STA bias margin of the 4-b parallel arithmetic logic unit (ALU) designed using the timing regulation scheme proposed in this article was increased by 5%, the PSCAN2 bias margin was increased by 7.4%, and 36 ps reduced latency. The ALU fabricated using the “SIMIT Nb03” process was successfully measured with correct operation at low frequency. It showed this scheme could provide accurate timing constraints range and enhances circuit bias margin.