A Static Timing Analysis Tool for RSFQ and ERSFQ Superconducting Digital Circuit Applications

Static timing analysis in the rapid-single-flux-quantum and energy-efficient RSFQ superconducting digital circuit domain is yet to be achieved in a generic sense. A static timing analysis tool is proposed here for preplacement designs as well as postplaced and routed designs. Preplaced static timing analysis attempts to find a general gauge for the performance of a JSIM/SPICE netlist in the absence of information on wiring delays. The postplaced and routed static timing analysis provides a more accurate analysis of a design in the cadence design exchange format. This design file should include all the wire lengths as well as a complete clocking scheme. Results of this postplaced and routed static timing analysis are then used to determine the maximum clock speed that the design can be run at to prevent timing violations. Results for both methods of analysis are presented and then incorporated in an hardware description language representation of the design to show that there are no timing violations at the presented clock speed. We show the implementation of a static timing analysis method developed as a precursor to the IARPA SuperTools project, and how it applies to circuits with H-tree and HL-tree clocking schemes.