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2023•Unpublished venueRequires access

An 8-bit 3.5 GS/s Current Steering DAC for Wireless Applications

Mohamed Taha, Khaled M. Morsi, Ahmed Naguib

Open publisher page 9 citations

Abstract

A segmented 8-bit 3.54 GS/s current-steering digital-to-analog converter (CSDAC) designed and simulated in 130 nm CMOS technology. The spurious-free dynamic range (SFDR) that represents the CSDAC linearity is ranged from 65.7 dB at 11 MHz signal frequency to 54 dB at 1.770 GHz with an effective number of bits (ENOB) equals to 7.97 bits at a low frequency while degraded across the input frequency to reach 7.67 bit at 1.77 GHz.

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What this paper is about

A segmented 8-bit 3.54 GS/s current-steering digital-to-analog converter (CSDAC) designed and simulated in 130 nm CMOS technology. The spurious-free dynamic range (SFDR) that represents the CSDAC linearity is ranged from 65.7 dB at 11 MHz signal frequency to 54 dB at 1.770 GHz with an effective number of bits (ENOB) equals to 7.97 bits at a low frequency while degraded across the input frequency to reach 7.67 bit at 1.77 GHz.

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OpenAlex reports 9 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Method / approach

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Available abstract

A segmented 8-bit 3.54 GS/s current-steering digital-to-analog converter (CSDAC) designed and simulated in 130 nm CMOS technology. The spurious-free dynamic range (SFDR) that represents the CSDAC linearity is ranged from 65.7 dB at 11 MHz signal frequency to 54 dB at 1.770 GHz with an effective number of bits (ENOB) equals to 7.97 bits at a low frequency while degraded across the input frequency to reach 7.67 bit at 1.77 GHz.

Key concepts: Spurious-free dynamic range, Effective number of bits, Bit (key), Linearity, CMOS, 12-bit, Electronic engineering, Dynamic range

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