Empirical Analysis of Side-Channel Attack Resistance of HLS-designed AES Circuits

Many IoT devices have been compromised by side-channel attacks. Among them, power analysis attack, which identifies the secret key of a circuit by analyzing the power consumption of the target device, is well-known. Although there is generally a trade-off between performance and hardware cost (resources) in circuits, the correlation between performance and security is not known. This study investigates the relationship between side-channel attack resistance, performance (clock cycles) and hardware resources of AES circuits. Six AES circuits with different performance are designed by high-level synthesis. T-test is employed to assess side-channel attack resistance. The results show that there is a correlation between side-channel attack resistance, performance and hardware resource usage, but the relationship varies depending on the definition of side-channel attack resistance.