Mapping DNNs onto a NoC-based MPSoC using synchronous dataflow graphs

This thesis discusses a framework to map and schedule the execution of irregular structured Deep Neural Networks (DNN) [1] onto a Network-on-Chip (NoC) based customizable heterogeneous Multiprocessor System-On-Chip (MP- SoC). This is the first work, to our knowledge, to do this by utilizing Synchronous Data Flow Graph (SDFG) [2]. First, we explore the irregularities in the architecture of modern DNN, such as LeNet-5 [3], AlexNet [4], DenseNet [5]. These models are typically defined using Tensorflow [6]. Next, we explore the rich semantics and expressive- ness of an SDFG to represent the execution of a DNN inferencing task. In order to use the SDF framework, we developed a tool to translate the DNN model description from last step into an SDFG, called an application graph. From these application graphs, we use the SDF3 tool [7] to analyze the theoretical maximum throughput achievable and conduct a search for a mapping of DNN layers to the tiles of a given hardware architecture graph representing a NoC-based MPSoC. For the sake of generality, we assume a heterogeneous MPSoC, in which there can be many tiles with different types of processor and memory sizes, placed in a mesh topology. As the original method of memory dimensioning implemented in SDF3 is inefficient when applied to this particular mapping problem, we developed a heuristic binary-search-based approach to search for the minimal memory distribution required to achieve a particular throughput constraint. Lastly, this thesis concludes with a discussion of several avenues that the work therein has opened up for further research.