Power estimation on hardware prototyping for MPSoC software

Advances in IC technologies have enabled embedded systems to use multi-processor system-on-chip (MPSOC) to meet the increasing performance demands. Since power is critical in mobile embedded systems, such as mobile phones, GPS navigation systems, digital cameras, and handheld DVD players, it is important to understand how power is consumed at the design stage of MPSOC-based embedded systems. Then, the power bottleneck of the design may be identified and improved for prolonged battery operations. In this thesis, we present a system-wide power estimation system for designing MPSOC-based embedded systems. This system can collect and accumulate hardware events of different system components, such as CPU, BUS, and memory, and then by coupling with related system power models, report the power consumption of application software. This system can be integrated into FPGA-based MPSOC design for fast power and performance evaluations. We will demonstrate the implementation of the system and show how it helps to collect power profile of an MPSOC system design.