On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really\n the Best Option?

Predictable execution time upon accessing shared memories in multi-core\nreal-time systems is a stringent requirement. A plethora of existing works\nfocus on the analysis of Double Data Rate Dynamic Random Access Memories (DDR\nDRAMs), or redesigning its memory to provide predictable memory behavior. In\nthis paper, we show that DDR DRAMs by construction suffer inherent limitations\nassociated with achieving such predictability. These limitations lead to 1)\nhighly variable access latencies that fluctuate based on various factors such\nas access patterns and memory state from previous accesses, and 2) overly\npessimistic latency bounds. As a result, DDR DRAMs can be ill-suited for some\nreal-time systems that mandate a strict predictable performance with tight\ntiming constraints. Targeting these systems, we promote an alternative off-chip\nmemory solution that is based on the emerging Reduced Latency DRAM (RLDRAM)\nprotocol, and propose a predictable memory controller (RLDC) managing accesses\nto this memory. Comparing with the state-of-the-art predictable DDR\ncontrollers, the proposed solution provides up to 11x less timing variability\nand 6.4x reduction in the worst case memory latency.\n