Carrier Mobility Analysis of Parallel Gated Junctionless Field Effect Transistor

The paper reports analysis of carrier mobility in a Parallel Gated Junctionless Field Effect Transistor. Fully analytical mathematical models for electron and hole mobilities are developed. The mobility models are developed using empirical relation between mobility and transverse and longitudinal electric field. The Quantum confinement effect has also been considered in the models. In the model electric field dependence on classical and quantum mechanical effects are formulated separately. The total electric field is the summation of the two. The models are compared with Technology Computer-Aided Design simulation results. The simulation results show that the parallel gated structure exhibits higher electron as well as hole mobility compared to that of a conventional Junctionless Field Effect Transistor. It can also be seen that the carrier mobility enhances with longer gap length due to reduced longitudinal electric field. As the models are analytical in nature and agree reasonably with numerical simulation results obtained from TCAD the models are suitable for compact modeling.