Coverage driven verification of linear feedback shift register hardware

The security of data transmission has become of utmost importance with rapid development in communication -and one of the essential parts of this is pseudorandom sequences.A pseudorandom sequence is a one which follows the property of random numbers, it can be classified under Deterministic Random Number Generator -which will generate the sequence algorithmically.There are various methods to generate the sequence -one of the efficient and faster method being Linear Feedback Shift Register.LFSR of n bit generates a maximum sequence of 2 n -1.This circuit operates on a feedback polynomial -which will decide the next sequence.The initial value, which is the seed, will start the stream of values produced by the register and this is determined by its current or previous state.This thesis presents a verification of design of LFSR using SystemVerilog to test the functionality and presents the results produced as part of the simulation.v