2022•2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)Requires access

Demonstration of Fatigue and Recovery Phenomena in Hf0.5Zr0.5O2-based 1T1C FeRAM Memory Arrays

Jun Okuno, Tsubasa Yonai, Takafumi Kunihiro, Kenta KONISHI, Monica Materano, Tarek Ali, Maximilian Lederer, Konrad Seidel, Thomas Mikolajick, Uwe Paul Schroeder, Masanori Tsukamoto, Taku Umebayashi

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Abstract

Recently, a novel, one-transistor one-capacitor (1T1C) type, ferroelectric random-access memory (FeRAM) array was developed, and its operation was experimentally demonstrated. This array was based on ferroelectric Hf0.5Zr0.5O2(HZO), with a capacitor under bitline structure, and was compatible with system-on-chip. In this work, bitline voltage difference distributions were examined via cycling tests and observed to not deteriorate during fatigue and recovery stress, indicating uniform charge trapping and domain de-pinning within the ferroelectric domains in the test chip.

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What this paper is about

Recently, a novel, one-transistor one-capacitor (1T1C) type, ferroelectric random-access memory (FeRAM) array was developed, and its operation was experimentally demonstrated. This array was based on ferroelectric Hf0.5Zr0.5O2(HZO), with a capacitor under bitline structure, and was compatible with system-on-chip. In this work, bitline voltage difference distributions were examined via cycling tests and observed to not deteriorate during fatigue and recovery stress, indicating uniform charge trapping and domain de-pinning within the ferroelectric domains in the test chip.

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Available abstract

Recently, a novel, one-transistor one-capacitor (1T1C) type, ferroelectric random-access memory (FeRAM) array was developed, and its operation was experimentally demonstrated. This array was based on ferroelectric Hf0.5Zr0.5O2(HZO), with a capacitor under bitline structure, and was compatible with system-on-chip. In this work, bitline voltage difference distributions were examined via cycling tests and observed to not deteriorate during fatigue and recovery stress, indicating uniform charge trapping and domain de-pinning within the ferroelectric domains in the test chip.

Key concepts: Ferroelectric RAM, Ferroelectricity, Capacitor, Chip, Materials science, Transistor, Ferroelectric capacitor, Optoelectronics

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