Static timing analysis of embedded software on advanced processor architectures

This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution time) and applicability of a methodology for modeling and analysis of instruction as well as data cache behavior. The second part of the paper proposes a timing analysis technique for super-scalar processors. The objects of our studies are two processors of the PowerPC family, in particular the PPC403 and the MPC750.