Synthesis for power-aware clock spines

Clock tree and clock mesh are two extreme structures of clock networks. Clock tree is good at saving clock wires and power, but is vulnerable to clock skew variation. On the other hand, clock mesh is good at mitigating clock skew variation, but spends considerable wires and power. Well known intermediate structures are clock tree with cross links and clock spine. This work addresses the problem automating the synthesis of clock spine networks. Unlike the clock tree with links between clock nodes, which is a sort of an incremental modification of the structure of clock tree, clock spine network is a completely separated structure from the structures of tree and mesh. Consequently, it is necessary and essential to develop a synthesis algorithm for clock spines, which will be compatible to the existing synthesis algorithms of clock trees and clock meshes. To this end, this work first addresses the problem of automating the synthesis of clock-gated clock spines with the objective of minimizing total clock power while meeting the clock skew and slew constraints. The key idea of our proposed synthesis algorithm is to identify and group the flip-flops with tight correlation of clock-gating operations together to form a spine while accurately predicting and maintaining clock skew and slew variations through the buffer insertion and stub allocation. Through experiments with benchmark circuits, it is shown our power-aware synthesis for clock spines uses significantly less power consumption compared to that of the conventional clock mesh synthesis algorithm at the expense of a little relaxed or the same constraint of clock skew.