High Performance Clock Path elements for Clock Skew reduction

this paper is presenting the findings of project work that involves finding more efficient and faster circuit logics to bring down the clock skew. Clock skew is the instantaneous difference between the readings of two clocks arrival time. Clocks are used to drive many individual units in a circuit i.e. they are required at many points throughout the circuit at the same time. The problems pertaining to transportation of clock signals are that a fraction of current reaches millions of transistors (because of fan-out) and the clock reaches far away units at a delayed time. Both these problems can be rectified by using efficient clock inverter and clock buffer circuits. Clock skew can be reduced by either increasing delay in the faster clock path to match the slower path or by reducing the delay in the slower path by improving driving strength. To match the arrival times, tunable clock buffers and clock inverters will be designed. This paper presents speed efficient circuits for clock buffers and clock inverters which can be implemented in the pre (clock tree synthesis stage) CTS. Pre and post layout analysis are done and results are obtained using cadence tools considering sample NOC router architecture. Clock buffer designed using gpdk 045 node and compared with the proposed clock buffer of 45 nm node. The timing slack of the designed standard cells improves by 45.9% and power consumption decreases by 2.09%.