Design and analysis of the HF-RISC processor targeting voltage scaling applications

This paper presents the design and analysis of HF-RISC, a 32-bit RISC processor, targeting voltage scaling applications. We start proposing a design flow that enables the processor to operate at multiple voltage levels and explore how this flow enables designers to leverage the advantages of low voltage designs. Next, we present a set of case study designs of HF-RISC in a 28nm FD-SOI technology assessing their area, performance and power figures. Using the collected data we discuss how our flow can enable better design space exploration for voltage scaling applications and define guidelines for achieving lower power and better power efficiency. Accordingly, the obtained results indicate that the proposed flow allows 9.5% lower power overall and 25.5% better energy efficiency in HF-RISC design.