Speed up techniques of logic simulation

This paper describes new simulation which reduce the computing requirement of a gate level logic simulator. The logic circuit to be simulated is transformed into the smaller one. The number of events as well as the storage necessary for expressing the logic circuits are decreased. Also, the evaluation of gates becomes faster by predicting whether a gate's input signal change would cause the gate's output signal change or not. Our simulator with these techniques has dealt with the logic of some 1,200,000 gates and has saved the computer processing time in developing our computer products.