An Improved Power Gating Technique with Data Retention and Clock Gating

The design of microelectronic power management circuits offering low power in sleep mode without degrading the performance in normal mode is stringent requirement for electronic systems design for IoT and other low power VLSI applications. The retention flip-flops are used to retain the state of a power gated combinational circuit when it enters in the SLEEP mode. In this research a improved technique to integrate power gating, data retention with additional clock gating is proposed. Further, we have analyzed power gating operation of a 4×4 array multiplier circuit with state retention in SLEEP mode along with additional clock gating operation for 32 nm and 45 nm technology nodes. The power saving analysis of a multiplier with power gating technique considering the sleep activity factor and data input frequency is also presented.