Synthesis of synchronous digital systems operating in double-edge of clock

In a synchronous digital system the activity of the clock signal is a major consumer of energy. It consumes 15% to 45% of energy consumed. Reducing the activity of the clock signal produces a reduction of energy considered, but also reduces clock skew problems and iteration electromagnetic. An interesting strategy is the synchronous digital system to operate in the transitions of both edges of the clock signal (double-edge triggered - DET), as this allows a 50% reduction in the frequency of the clock signal, but having the same processing rate data. In this paper we propose a method for synthesis of synchronous digital systems that operate on both edges of the clock signal, but the state memory is composed only of flip-flops that are sensitive to a single edge of the clock signal (single-edge triggered flip-flops - SET-FF).