Design and Analysis of Improved Low Power and High-Speed N-Bit Adder

An adder is one of the essential blocks in all digital designs. By effectively modifying the transistor count, we can obtain better results in VLSI circuits. In this paper, an improved version of high speed low-power n-bit ripple carry adder design is proposed. Here, a new design technique is used in which, instead of replicating the adder cell n-times as in conventional ripple carry adder, two 14-transistor adder cells are repeated alternatively. These two adder cells are complemented each other. In the sense that, the first adder module produces an inverted carry-out, and this will act as a carry input to the second module and it will produce a non-inverted carry-out. In this manner, the two-bit addition will be carried out. By this technique, it will successfully embed the buffer in the critical path and the transistors involved in this virtual buffer share the sum and carry functionality generation accordingly. Owing to this functionality, it achieves low power, high speed full, swing output, less transistor count and high drivability. This design is simulated in 90nm-technology and it has the feature of operating at low supply voltage 10V. At the end of this work the comparison is carried out with the existing address designs.