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2003•Unpublished venueRequires access

Fast carry-look-ahead adder

Kaamran Raahemifar, Majid Ahmadi

Open publisher page 11 citations

Abstract

This paper presents a high-speed VLSI implementation structure for adder. Innovative serial implementations of carry-look-ahead adders ore developed. The critical path in CLA adders, where the carry is propagated, is implemented using a parallel structure. The supply voltage (V/sub dd/) is 3.9 v which con be lowered to 2.5 v. The adder is in 0.8 /spl mu/m technology. HSPICE simulation shows a total delay of 1.2 ns for 32-bits CLA adder.

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What this paper is about

This paper presents a high-speed VLSI implementation structure for adder. Innovative serial implementations of carry-look-ahead adders ore developed. The critical path in CLA adders, where the carry is propagated, is implemented using a parallel structure. The supply voltage (V/sub dd/) is 3.9 v which con be lowered to 2.5 v. The adder is in 0.8 /spl mu/m technology. HSPICE simulation shows a total delay of 1.2 ns for 32-bits CLA adder.

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Available abstract

This paper presents a high-speed VLSI implementation structure for adder. Innovative serial implementations of carry-look-ahead adders ore developed. The critical path in CLA adders, where the carry is propagated, is implemented using a parallel structure. The supply voltage (V/sub dd/) is 3.9 v which con be lowered to 2.5 v. The adder is in 0.8 /spl mu/m technology. HSPICE simulation shows a total delay of 1.2 ns for 32-bits CLA adder.

Key concepts: Adder, Carry (investment), Carry-save adder, Serial binary adder, Computer science, Very-large-scale integration, Arithmetic, Parallel computing

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