Lim, Khoon Aun.
Abstract
This thesis pertains to design and analysis of a 16-bit low-voltage (1.1 V) low-power asynchronous parallel multiplier targeted for a low-power asynchronous digital signal processor.
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This thesis pertains to design and analysis of a 16-bit low-voltage (1.1 V) low-power asynchronous parallel multiplier targeted for a low-power asynchronous digital signal processor.
Key concepts: Multiplier (economics), Asynchronous communication, Computer science, Economics, Telecommunications, Keynesian economics