Error-tolerant multiplier for high speed application

With the advent of hand held computing devices that require functionality rivaling the desktop, low-power and high-performance systems have become very important.The transistor network contributes mostly to the overall power dissipation and is becoming a major obstacle in implementing those systems.Hence, the need for high performance basic sequential element with low-power dissipation is steadily growing.The aim of this project is to develop a new type of multiplier to fulfill this need.In this report, for the first time, a multiplier design concept that engages accuracy as a design parameter is proposed.By introducing accuracy as a design parameter, we can break-through the bottleneck of conventional digital IC design techniques to improve on the performances of power consumption and speed.The two dimensional trade-off between power and speed becomes three-dimensional, i.e. power-speed-accuracy.To realize the design concept, digital multiplier circuits were studied and a novel mechanism is proposed in this work.The new type of multiplier adopting the proposed mechanism is named Error-Tolerant Multiplier (also called ETM).As illustration, the designs of 8-bit and 12-bit Error-Tolerant Multiplier, taken as examples, are described to elaborate on the design process and detailed circuit implementation of an ETM.ETM is a novel design of low-power and high-performance multiplier based on the technique of statistically analysis on the error compensation for truncated partial products.It offers significant reduction in power consumption as well as for the improvement of circuit delays with small gate area usage.Both the output stage and performance of the new ETM was studied and compared with existing standard multipliers.All the tests performed in this research were conducted using the SPECTRE simulation tool of the CADENCE software.With this tool, substantial four to six times improvement was noted especially in the power-delay-product (PDP), when compared to conventional multiplier configurations.