Implementation of Reconfigurable Data Encryption Technique using different AES versions

The Advanced Encryption Standard is widely used for encrypting data today. Unauthorized individuals will not be able to access data encrypted using AES. This paper presents the implementation of three different variants of AES in FPGA using Reconfiguration. The hardware utilization is a major factor considered to reduce the area used on a chip and thus the system cost. Using the reconfiguration feature of the FPGA, the different AES versions implemented can be loaded as and when required with reduced hardware utilization.