Low Power 10-bit 100 MSPS Segmented Current Steering DAC with > 78 dB SFDR

In this paper, High static and dynamic performance low power 100 MSPS 10-bit segmented Current Steering DAC (CS-DAC) is presented. This proposed DAC is designed using 130nm CMOS technology for wireless communications. The proposed DAC architecture follows 3+3+4 segmentations, in which 6 MSB bits are realized with unary DACs, and 4 LSB bits are realized with binary DAC structure. To improve the static and dynamic performance, re-timing latches and Cascoded current cell used, respectively. The proposed DAC, Spurious Free Dynamic Range (SFDR) is > 78 dB for signal frequency up to 33.5 MHz. Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL) of this DAC is 0.25 LSB and 0.0912 LSB, respectively. The current consumption of this DAC is 1.75 mA at 1.2 V supply.