2021IEEE Transactions on Electron DevicesOpen access

ULTRARAM: Toward the Development of a III–V Semiconductor, Nonvolatile, Random Access Memory

Dominic Lane, Peter Hodgson, Richard J. Potter, Richard Beanland, M. Hayne

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Abstract

ULTRARAM is a III-V compound semiconductor memory concept that exploits quantum resonant tunneling to achieve nonvolatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2×2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500- μs duration, a remarkable switching speed for a 20 μm gate length. Memory retention is tested for 8×104s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8×104readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for $10^{6}$ cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105half-voltage cycles.

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ULTRARAM is a III-V compound semiconductor memory concept that exploits quantum resonant tunneling to achieve nonvolatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2×2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500- μs duration, a remarkable switching speed for a 20 μm gate length. Memory retention is tested for 8×104s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8×104readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for $10^{6}$ cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105half-voltage cycles.

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Available abstract

ULTRARAM is a III-V compound semiconductor memory concept that exploits quantum resonant tunneling to achieve nonvolatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2×2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500- μs duration, a remarkable switching speed for a 20 μm gate length. Memory retention is tested for 8×104s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8×104readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for $10^{6}$ cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105half-voltage cycles.

Key concepts: Quantum tunnelling, Non-volatile memory, Physics, Optoelectronics, Computer science, Electrical engineering, Topology (electrical circuits), Engineering

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