A Novel Approach of ONOFIC Method to the Minimization of Leakage Power in CMOS Circuits

This paper deals with the leakage power problem in CMOS circuits, most of the time maximum power dissipation in the case of batteries using applications effected by varying the parameters like cost and reliability, etc. in this maximum power dissipation cases which is leakage power is a major parameter in design aspects. The proposed technique is to reduce the power leakage in CMOS circuit design. In this paper, it highlighted those universal logic circuits and other logic operations to exhibit the effect of power leakage reduction in the CMOS circuits we proposed ONOFIC method has comparatively good results with conventional techniques like LCNT and LECTOR all logic circuits have stimulated by using the tanner tool Nanometer technology.